EEL 6323 – Advanced VLSI Design
January February March April May	Current Assignments: Project submission: 1. E-mail your TA and instructor a pdf copy of your 4-page paper by 5:00pm on Thursday. If you do not have access to a pdf distiller, simply drop off a hard copy in NEB 527. 2. Remember to also send the DRC and LVS reports. Download the project grading plan here Week 15: 04/21 Classes End Week 15: 04/14 Process Skew Compensation Input/Ouput (IOs) and Transmission Lines Memory Week 14: 04/07 Clock distribution and Sequencing (Ch 7 W&H) Process Skew Compensation Week 13: 03/31 Clock distribution and Sequencing (Ch 7 W&H) Week 12: 03/24 Clock distribution and Sequencing (Ch 7 W&H) Download your Final Project assignment Due May 1^st, 2008 EXAM on March 26th Week 11: 03/17 Finish-up adders Download HW6 (due March 24) PROJECT #5 DELIVERABLES: 1. 4-page paper 2. It is assumed that your layout must be DRC clean and must match LVS. To ensure this is the case, please also hand in your DRC and LVS log files. 3. Your layout should be included in your paper Week 10: 03/10 Spring Break Week 9: 03/02 Finish up Dynamic Circuits Adders next (Ch. 10 of W&H) Midterm EXAM: Date: Wed March 26 Time: 8:20PM – 10:10PM Location: LAR 310 NEW HW#5 Due date: March 17th Week 8: 02/25 Finish up power dissipation Circuit Families (Ch. 6 of W&H) HW5 assigned (due date March 7^th) Week 7: 02/18 More on power dissipation Project is DUE on Monday 25. PROJECT DELIVERABLES: List all the assumptions supported with explanations. Give a brief description of how your program works. In addition, include the following: 4. VHDL code 5. TEST_BENCH and results of all the cases. 6. Gate-Level schematic after synthesis (Simulations after synthesis not required). 7. Layout. 8. DRC clean report. 9. LVS report. 10. final.v after the PAR step. 11. number of gates in the final.v file (NAND NORS and so on) 12. Area of the layout in um2 (show it on the layout) Check here for FAQ Week 6: 02/11 Logical Effort Power dissipation Download HW4 and associated scripts (you will have to unzip the files) HW4 due Feb 25th Week 5: 02/04 Digital Design Flow HW3 due Feb 8th Week 4: 01/28 Reading: Ch4 Logical Effort Week 3: 01/21 Reading: Ch2 & 5 W&H HW2 due Jan 30 Week 2: 01/14 Reading: Ch2 & 3 W&H HW1 due Jan 18 Down load a cadence printing tutorial Week 1: 01/07 Classes Begin: Jan 07 Reading: Ch1 W&H
Syllabus	Notes: Tutoring is offered through the UF Teaching Center for Electronics I in SW Broward Hall - see http://www.teachingcenter.ufl.edu Times: http://www.teachingcenter.ufl.edu/hours_location.html